Drawingboard ii, a graphical input-output device for a computer

ABSTRACT

A two-dimensional matrix of semi-conductors is arranged in ordered array as a flat, light emitting and light sensing device activated both electrically and by radiant energy from a penlight to achieve a graphical input and output display by the active or inactive condition of the light emitter with circuitry for control of flow of graphical data into and out of the device for use in conjunction with a digital computer.

United States Patent Graven [451 June 27, 1972 [72] Inventor: RobertMichael Graven, 203 Holly Lane,

Orinda, Calif. 94563 [22] Filed: Aug. 26, 1970 [21] Appl. No.: 70,626

52 U.S. CI. ..340/173 LS, 250/213 A, 340/324 A, 340 1725 51 Int. Cl..G11c 13/04 [58] Field ofSearch .250/213 A,214 P,217 ss; 340/324 R,172.5

[56] References Cited UNITED STATES PATENTS 3,309,712 3 19'67 Cole ..340324 R 3,364,473 1/1968 Reitz ..340/l 72.5 3,559,182 2/1971 Floret..340/324 A 3,559,307 2/1971 Barrekette .....340/324 A 3,579,225 5/1971Clark ..340/324 A Primary Examiner-Terrell W. Fears Attomey-Robert '1'.Tipton ABSTRACT A two-dimensional matrix of semi-conductors is arrangedin ordered array as a flat, light emitting and light sensing deviceactivated both electrically and by radiant energy from a penlight toachieve a graphical input and output display by the active or inactivecondition of the light emitter with circuitry for control of flow ofgraphical data into and out of the device for use in conjunction with adigital computer.

33 Clains, 24 Drawing Figures 3,673,579 sum us I 15 PATENTEDJum I972P'ATENTEnJum I972 sum 07 or 15 IN VENTOR.

JROBERT M. GRAVEN BY W - fi i DRAWINGBOARD u, A GRAPHICAL INPUT-OUTPUTDEVICE FOR A COMPUTER BACKGROUND OF THE INVENTION This invention relatesgenerally to registers and in particular to electrical calculators ofthe hybred type.

Various devices have been used in the past for placing graphical datainto a computer and for display of graphical data generated by acomputer.

Cathode ray tube displays have been used with a light pen having a photosensitive cell directed at the display on the surface of the tube topick out or place a point in the display.

Other devices use a flat matrix of electrical terminals which areconnected to a computer and a metal stylus also connected to thecomputer which acts as a writing instrument when applied to and tracedacross the surface of the matrix.

Still other devices use photosensitive materials for receivinginformation but do not display information back from the same plane ofthe device after it is entered or processed by the computenFew of thegraphical input-output devices of the prior art provide circuitry whichcan control the flow of graphical information into and out of the devicewhich is separate and apart from the computer.

SUMMARY OF THE INVENTION The device of the present invention is a flatgraphical inputoutput device for a computer using light sensors toreceive information, with light emitters juxtaposed adjacentcorresponding sensors to display information. A penlight, i.e., a pen orlight emitting writing instrument, is held inthe hand of the operatorand is used to activate the light sensors. A processor unit is used tocontrol the flow of information into and out of the device for operationwith a computer. The processor unit circuitry provides for activating,deactivating and determining the status of each emitter in accordancewith either a coded or uncoded signal. The processor unit also isarranged to activate rows, columns and blocks of emitters as desired.

It is, therefore, an object of the present invention to provide agraphical input-output device for a computer.

It is another object of the present invention to provide a graphicalinput-output device for a computer having individual point control usinga coded or uncoded address.

It is still another object of this invention to provide a graphicalinput-output device for a computer in which the flow of information intoand out of the device is separately controlled.

It is another object of this invention to provide a graphicalinput-output device for a computer in which logical information isassociated with the positional information in the graphical display.

It is another object of this invention to provide a graphicalinput-output device for a computer in which a penlight is used forgraphical input.

It is another object of the present invention to provide a graphicalinput-output device for a computer in which photon output of thepenlight is controllable for shading the graphical input and output.

It is another object of the present invention to provide a graphicalinput-output device for a computer in which the photon output of thegraphical display is controllable for information output.

It is still another object of the present invention to provide agraphical input-output device for a computer having apparatus forperforming programmed switching routines for special displays, operatingcommands and manipulation of graphical data.

Other and more particular objects of the present invention will bemanifest upon study of the following detailed description when takentogether with the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an isometric view of thegraphical input-output device of the present invention,

FIG. 2 is a plan and elevational view of a typical emittersensor pair,

FIG. 3 is a logic diagram of a typical point defined by a lightemitter-sensor pair,

FIG. 3A is a more detailed circuit diagram of a typical point,

FIG. 4 is a symbol list defining some of the symbols used in thedrawings,

FIGS. 5A and 5B is a single line block diagram of the circuitry of thepresent invention showing the interconnection of the various controlunits used to operate the device,

FIG. 6 is a circuit diagram showing the connection of primary inputregister, operations decoder, B. AND and C AND gates, local memory, FAND and G OR gates, and memory OR gates,

FIG. 7 is a circuit diagram of control registers SR( 0) through SR(3) ofthe drawingboard processor unit,

FIG. 8 is a circuit diagram of control registers SR( 4) through SR( 6)of drawingboard processor unit,

FIG. 9 is a circuit diagram of the W control gates of the drawingboardprocessor unit,

FIG. 10 is a circuit of the X-input, X-output and X-parts registers asconnected to the drawingboard,

FIG. 11 is a circuit diagram of the Y-output register and the XY-, Z'-,and the Z-registers for transmitting the graphical information to thecomputer,

FIG. 12 is an elevational view of a typical penlight used to placeinfon'nation into and erase information from the graphical device ofFIG. 1 along with details of circuitry for connecting it to the device,

FIG. 13 is a circuit diagram of the input character gates register ofthe drawingboard processor unit,

FIG. 14 is a circuit diagram of an instruction logic device used tomeasure incremental variations in the graphical disp y.

FIG. 14A is a circuit diagram of a typical timing chain device used inFIG. 14,

FIG. 14B is a circuit diagram of a device to direct X- and Y- adders toadd or subtract one binary digit from the address,

FIG. 15 is a diagram of typical pulse wave forms of the timing device ofFIGS. 14, 14A and 14B.

FIG. 16 is a circuit diagram of a comer of the array showing a typicalpoint and its interface with peripheral circuitry to the board.

FIG. 17 is a circuit diagram showing the X-decoder in greater detail,

FIG. 18 is a circuit diagram showing the Y-decoder in greater detail,

FIG. 19 is a circuit diagram showing the X-encoder in greater detail,

FIG. 20 is a circuit diagram showing the Y-encoder in greater detail.

DESCRIPTION OF THE PREFERRED EMBODIMENT With reference to FIG. 1, thegraphical input-output device of the present invention comprises,basically, a write and display board 20, i.e., input-output drawingboard20, which is mounted on an electronic and power supply cabinet 21 havinga control panel 22 on the front thereof.

A penlight 23 is electronically connected to board 20 by two or moreconductors 86 and 86', 24 and 25 for control of the light output of thepenlight as will be described below, and for control of informationplaced in the board. Board 20 further comprises modular emitter-sensorcircuit units or points 26 shown typically in FIGS. 2 and 3 arranged inan array 35 (FIG. 1) of horizontal and vertical rows and columnsrespectively.

Referring to FIG. 2, a modular emitter-sensor pair or point 26 is shownin plan and elevation and comprises a compartment in block 27 containinglocal circuitry, on the top surface of which is mounted a light emitter28 and a light sensor 29 along with other light sensors furtherdescribed below. Light emitters 28 may be any light emitting means suchas an incandescent or neon glow lamp, however, the present device isarranged to utilize a semi-conductor device such as a light emittingdiode common in the art.

Light sensor 29 is, as used in the present embodiment, a semi-conductordevice sensitive to electromagnetic radiation.

To protect emitter 28 and sensor 29 from damage, a transparent surface30 is disposed over the entire surface of array 35.

FIG. 3 illustrates a simplified logic diagram for a typical point i.e.,emitter-sensor pair circuit 26. Such a point" 26 comprises an X-sensediode 31 connected on its anode side to X-conductor 32 and a Y-sensediode 33 connected on its anode side to Y-conductor 34. The cathodesides of X- and Y- sensediodes 31 and 32 are connected in common to theoutput of AND gate 36 and the output of light sensor 29 through pointingcircuit 50.

Light emitting diode 28 and one of the inputs to AND gate 36 areconnected to the output of memory circuit 37. The other input of ANDgate 36 is connected to READ conductor 38 while the two inputs to memorycircuit 37 are connected to WRITE conductor 39 and ERASE conductor 40.

With reference to FIG. 3A, a more detailed circuit diagram of a typicalpoint 26 is shown.

The reference numerals of corresponding parts of the circuit of FIG. 3and 3A are identical.

The identification of each circuit .element and its value, whereapplicable, is listed in Table 1. The number-letter combination underTypeis the present industrial standard designation for thesemi-conductor device used.

Table 2 is a listing of the values for resistors 172 and 173 necessaryto change the state of the bi-stable circuit of FIG. 3A. The sensitivityrange is generally descriptive. The measured values would range fromabout 100 foot-candles for an intenselight to about 0.5 foot-candles forshadow light.

TABLE 1 Ref. No. Type or Value Purpose 160 2N22 19 Computer writetransistor 161 2N22l9 Computer erase transistor 162 IN 2175 Opticalwrite transistor 163 1N2175 Optical erase transistor 164 2N3l35Bi-stable pnp transistor (for memory) 165 2N22l9 Bi-stable npntransistor (for memory) 166 2N22l9 Driver transistor 29 1N2 175 Opticalpointing transistor 167 2N4409 Inverting driver transistor 28 MVEIOOLight emitting diode 169 1N643 Bias diode 170 1N643 Bias diode 1711N56AG Isolating diode 33 1N56AG Y-sense diode 31 1N56AG X-sense diode172 K Enable sensitivity resistor 173 10 K Disable sensitivity resistor174 100 ohms Light emitting diode (LED) current limiting resistor 175 10K Transistor 166 current limiting resistor 176 10 K Bias resistor 177 1K Transistor 167 current limiting resistor 36 SN7402 NOR gate Table 2Value of Resistors Light Level l72'and 173 l K Intense 10 K Room lamp100 K Dim 1 Meg Shadow From FIG. 3A," WRITE conductor 39 enters circuit26 through transistor 160 while ERASE conductor 40 enters the circuitthrough transistor 161 for computer control of the WRITE-ERASE function.The same function can be performed using penlight 23 by activating lightsensor 162 to write or light sensor 163 to erase.

Memory is achieved through bi-stable transistors 164 and 165 which lockin the on or ofi' status ofthe point, i.e., whether or not a current isflowing through light emitting diode 28.

To activate the point, penlight 23 is pointed at light sensingtransistor 162 and light sources 88 (FIG. 12) are energized to shine onsensor 162 causing a current to flow through the transistor, applying avoltage to one side of light emitting diode 28 causing a current to flowtherethrough.

To deactivate the point, penlight 23 is pointed at light sensingtransistor 163 and light sources 88 are energized to shine on sensor 163reducing its resistance to a value sufficient to lower the voltageacross light emitting diode-28 to limit the current therethroughsufiicient to turn diode 28 off.

For consistency and understanding of thedrawings, FIG. 4 defines thesymbols used in the drawings.

OR gate 41 of FIG. 4 is a semi-conductor device having two or moreinputs and one output. A signal, i.e., a voltage pulse, on either of theinputs on the left will appear on the output (right) side of the device.AND gate 42 of FIG. 4 is a semiconductor device having two inputs, bothof which must be activated, i.e., have a voltage on the inputconductors, for a signal to appear on the output side.

Dtype flip-flop 43 is a bi-stable semi-conductor device having a signalinput 44 and a clock" input 45, a reset input 46 and two logicalcomplimentary out-put conductors 47 and 48.

Activation of clock input 45 will permit a signal on input 44 to pass tooutput conductors 47 and 48.

Activation of reset input 46 causes all flip-flops 43 to return to alogical zero or ofi"position.

Inverting amplifier 49 is a device common in the art for producing thelogical compliment of a digital signal.

With respect to the entire system, FIGS. 5A and 58, shown on two sheets,is a single line block diagram showing theinterconnection of the basicelectronic switching units which serve to control the How of informationinto drawingboard 20 and also to and from the computer (not shown)through drawingboard 20 for the manipulation of the data containedtherein.

The computer that is used in conjunction with the device of the presentinvention can be any digital computer common in the art which canreceive, manipulate and transmit informationcoded in a manner toidentify individual bits of information, for example, in the form ofvoltage pulses on various combinations of conductors or lines leadinginto and out of the present device.

The blocks in FIGS. 5A and SBrepresent switching circuits which comprisebasically combinations of ANDand ORgates and flip-flop devices with theexception of local memory 106 which may be any type of device common inthe art which can temporarily store information. A magnetic core memorycommon in the art would be one example.

With particular reference to FIG. 5A, there is illustrated the circuitsassociated with drawingboard 20 used to place information into the boardand read information stored in the board.

Basically, drawingboard 20 comprises a 16 by l6 array 35 of points" 26having sixteen X-conductors 32 (FIG. 3 and 3A) arranged parallel andequally spaced in a common plane with sixteen Y-conductors 34 arrangedparallel and equally spaced normal to X-conductors 32 in said commonplane.

A point26 is connected at the intersection of each X- and Y-conductor 32and 34, respectively.

Array 35, therefore, comprises 256 "points" 26 arranged in 16 horizontaland 16 vertical rows and columns, with each point" 26 comprising theelements of the circuit of FIG. 3A. FIG. 16 shows array 35 comprisingread, write and erase gate registers 154, and 156, respectively, whoseoutputs are connected to conductors 38, 39 and 40 through read, writeand erase point AND gates 157, 158, and 159, respectively.

Thus activation of any of the conductors 38, 39 M40 will cause data inarray 35 to be, respectively, read written, or erased by the computer(not shown) from array 35.

It will be noted that through the use of penlight 23, as previouslydiscussed and shown in FIG. 3A, an individual point" 26, may be read,written or erased by appropriate photoactivation of transistors 29, 162or 163, respectively.

To the left and bottom of array 35 (FIG. 5A) are input sides 53Y and53X. To the right and top of array 35 are the output sides 54Y and 54X.

The input circuitry for the device of the present invention comprises,for the X-sense (x-coordinate), X-input register 56 whose output isconnected to X-input side 53X, X-input parts register 57 whose output isconnected to the input side of X-input register 56 and whose variousinputs are connected to drawingboard processor unit 100 (FIG. 5B).

The output of X-address decoder 58 is connected to the input of X-inputparts register 57 while the input side of X-address decoder 58 isconnected through XCD gates 115 to drawing board processor unit 100(FIG. 5B).

In a like manner for the Y-sense (Y-coordinate), the output side ofY-input register 60 is connected to input side 53Y of array 35 while theinput side of register 60 is connected to the output side of Y-inputparts register 61. The output of Y-address decoder 62 is connected tothe input side of Y-input parts register 61 while the inputs of bothY-address decoder 62 (through YDC gates 120) and Y-input parts register61 are connected to drawingboard proccessor unit 100.

The output circuitry for the device of the present invention comprises,for the X-sense (X-coordinate), X-output register 64 whose input isconnected to X-output side 54X, X-output parts register 65 whose inputis connected to the output of X- output register 64.

It will be noted that the output of X-output register 64 is alsoconnected to the input of X-address encoder 66 whose output is connectedboth to multiple input OR gate XOOR 150 and XEC gates register 81 (FIG.17).

In a like manner, for the Y-sense (Y-coordinate), the input side ofY-output register 68 is connected to Y-output side 54Y, while its outputside is connected to the input side of Y- output pans register 69.

It will also be noted that the output of Y-output register 68 isconnected to the input of Y-address encoder 70 whose output is connectedboth to multiple input OR gate YOOR 151 and YEC gates register 124 (FIG.18).

Both X- and Y-output parts registers 65 and 69 are connected todrawingboard output register 73 whose output is connected to thecomputer (not shown).

All registers, it will be noted, are connected to drawingboard processorunit 100.

DRAWINGBOARD PROCESSOR UNIT FIG. 5B shows the interconnection of thevarious block circuits contained in the drawingboard processor unit 100.

Basically, drawing board processor unit 100 comprises a primary inputregister 101, whose outputis variously connected to operations decoder102, C AND gates register 103, B ANDgates register 104 and instructionlogic circuit 152.

Operations decoder 102 is variously connected to local memory 106, F ANDgates register 107, address code status register SR() 108, input partstatus register 812(1) 109, output parts status register SR(2)110, readstatus status register SR(3)111, labels" status register SR(4) 112,location storagestatus register SR()113, and memory bufferstatusregister SR(6) 114 and instruction logic circuit 152.

Drawingboard processor unit 100 further comprises, input character gatesregister 116, W gates register 117, 6" OR gates register 118, and memoryOR gates register MOR 1 19.

To describe the device of the present invention in detail, certainconventions will be used to organize the material. The letters AthroughZ are used to identify the lines or circuitsinterconnecting the variouscircuit units or blocks. For example, line A( 1) designates line "1 ofcircuit "A," X(07)designateslines 0 (zero)through "7 of circuit X.

Certain abbreviations may be used which will be self evident such as XIIfor X-inputs parts register; YOP" for Y-output parts register and SR forstatus register.

Since certain commands are required for various control functions, theseare designated by the command number contained in a circle when shown onthe drawings and preceded by an asterisk when discussed in thespecification. For example, a command identified by 03" in a circle on adrawing is identified as *03" in the specification.

The arrows which are incorporated into the circuit lines represent theflow of information or data through drawingboard 20 and processor unitin accordance with the direction of the arrow.

As for detailed discussion of the circuit units of the presentinvention, it is apparent to one skilled in the art that the use of ANDgates, OR gates and flip-flop devices in switching circuits is common inthe art and the function of each individual circuit element can befollowed by such person without further detailed explanation.

To describe in detail the individual circuit units of drawingboardprocessor unit 100, reference is made to FIG. 6 and beginning inparticular to primary input register 101.

Primary input register 101 comprises a plurality, sixteen in the presentembodiment, of flip-flop circuit units 121 having outputs A(0) throughA( 15). The input signal enters register 101 in a manner such that thefust five bits," A(0) through A(4) of information are an encoded commandsignal; the next three bits, A(5), A(6), and A(7) are an encodedinstructional signal also identified as lines [(0), I( 1) and K2),respectively; and the remaining eight bits are an encoded X-Y addresssignal for a particular point" 26, four bitsfor the X-address and fourbits for the Y-address.

Operations decoder 102 comprises a set of input OR gates 122, a decoderunit common in the art which converts the on or ofFstatus of eitherlines A(0-4) or E(0-4) to a pulse or signal on any one of 00 to 37(octal) outputs on 32 lines (decimal).

Command lines *01 through *37 are connected to the registers for controlof array 35 The detailed operation of each command is described supra. I

B AND gates register 104 is used to bypass coded adderess informationaround local memory 106 while C AND gates register 103 is used to placecoded address information into local memory 106.

The output of lines A(7) (also identified as line I(2)) and A'(7) of theinstructional coded section of primary input register 101 are used togate the flow of information through C and B"gates registers 103 and 104respectively. The signal on line A'(7) is the logical compliment of thesignal on line A(7 Local memory 106 can be any memory unit common in theart for storing bits" of information such as a magnetic core matrix andthe like common in the art.

Local memory OR gates register MOR 119 comprises eight OR gates whichcontrol the flow of information from memory 106, instruction logiccircuit 152 and B AND gates register 104into lines X'(0-3) and Y'(0-3).

F AND gates register 107 comprises all AND gates 134 and G OR gatesregister 118 comprising all OR gates 135 are used to control the flow ofinformation into memory buffer" status register SR(6) 1 14 (FIG. 5B).

With reference to FIGS. 7 and 8, there is shown the detailed circuitdiagram for status registers SR(0) through SR(6) reference numerals 108through 1 14, respectively.

Basically, each status register comprises a column of bi-stableflip-flop devices and a column of AND gates 126.

Typically, two command lines 127 and 128 are connected to flip-flopdevices 125. Line 127 is connected in common to the clock inputterminals of each flip-flop device 125 for the purpose of transferringthe status of the signal input lines into the register, and the othercommand line 128 is connected in common to the reset input of flip-flopdevices 125 to reset all flip-flop devices to a logical zero orofl"status.

It will be noted that AND gates 126 are used to gate information out ofthestatus registers upon appropriate activation of lines RSW(-7) ofstatus register SR(3) 1 11.

Status registers SR(0-6), reference numerals 108 through 1 14, areidentified as shown in Table 3 as follows:

3 memory bufier" codes With reference to FIG. 13, there is shown thedetailed circuit diagram for character gates register 116 whichcomprises 32 AND gates 130.

Register 116 converts the coded address of a typical point26.. on linesX'(0-3) and Y(03) to activation of lines X(0-15) and Y(015) byappropriate activation of lines XIC(O-l and YIC(0-l For example,concurrent activation of lines Y(2) and XIC( 1) will causeline X(l4) tobe activated.

FIG. 9 illustrates a detailed circuit diagram of W gates register-117which coi'nprises eight lower OR gates 132 and eight upper OR gates 133.The lower OR gates 132 have input and output lines as tabulated in Table4. The upper OR gates 133 have input and output lines as tabulated inTable 5.

TABLE4 Output Input Lines Lines W), W), 0( m) m) U). H). (1). 0), 0( U)U) L( 0), 0), G), 0( 0) M 0). C), H 0( H H). M); 0( 6), W 0(5), U (6).H6), 0(6). R( 0 0( (7)' TABLES Output input Lines Lines U- 11(8), 0) O).0 0 0 U W U W 0 0 0), 0 (6) 0 (l5). R(

DRAWINGBOARD With reference now to FIGS. and 11, FIG. 10 is a logicdiagram of the input andoutput register circuits for drawingboard 20.The input and output register circuits in the Y- direction are identicalto those in the X-direction and, therefore, are not repeated in thedrawing. Discussion of the X- input and output circuitry applies as wellto the Y-input and output circuitry. FIG. 11 is a circuit diagram ofdrawing board 8 output register 73 as well asa circuit diagram ofY-output register 68 and Y-output parts register 69.

Referring-to FIG. 10, X-input parts gate register 57 comprises a set ofsixteen X-parts ANDgates 75 and a set of six- 1 teen X-parts OR gates76.

One side of the input to AND gates 75 is connected consecutively ingroups of four, to lines X'(O-3). The other side of the input to ANDgates75 is connected in common, in groups of four, to lines XIP(0-3). Itcan be seen, using this arrangement, that by selective activation oflines X'(0-3) and XIP(0-3), only one line or a combination of linesX(0-'l5) can be activated. Thus, combined with the Y-direction, onepoint or combination of points will be activated.

Input register 56 comprises sixteen bi-stable flip-flop devices 77 whichact to control the flow of the information on the output lines 78 ofinput parts register 57 into array 35.

Command lines *01 and *02 for the X- and Y-coordinates are used tocontrol the flow of such information. Command lines *10 and *11 (FIG.5A)are used to reset X-input register 56 and Y-input register60,.respectively, to a logical zero of ofi'"status.

X-output register 64, similar to X-input register 56 comprises sixteenbi-stable flip-flop devices 79 which act to control the flow ofinformation out of array 35.

Line ROR to X- and Y-output registers 64 and 68 from OR gate 145 (FIG.12) is used to control the flow of output information. Command lines *13and *14 (FIG. 5A) are used to reset X-output register 64 and Y-outputregister 68, respectively, to a logical zero or off" status.

X-output pans gate register 65 comprises all AND gates 80. It will benoted that one side of the input to AND gates 80 is connected in common,in groups of four, to lines XOP(0-3). Thus by appropriate activation oflines XOP(03), information is gated out of X-output register 64 intodrawingboard output register 73 (FIG. 1 1

Referring to FIG. 1 l, drawingboard output register 73 comprises XY ORgates register 82, Z-OR gates register 83 and Z- output register 84which is connected to Y-output parts gate register 69 and X-output partsgate register 65 at the input side of XY OR gate register 82.

. Z-output register 84 comprises sixteen bi-stable flip-flop devices 85used to transfer information from its input side to the computer (notshown). Command line *06 is used to con.- trol the flow of theinformation to the computer while command line *15 is used to reset allthe bits of output register 84 to a logical zero or ofi state.

With reference to FIG. 5A and in particular to X-address decoder 58,Y-address decoder 62, X-address encoder 66 and Y-address encoder 70, thecircuitry for these devices is common in the art and comprises AND gatesY DC 120, XDC 1 I5, YEC 124 and XEC 81 and inverting amplifiers suchthat the "on and off status combination of four input lines intoaddressdecoders 58 and 62 causes activation of only one of 16 output lines ofthe decoder, and for encoder 66 or 70, activation on one of 16 inputlines causes a particular combination of on-off states of four outputlines of the encoder.

Typically in FIG. 19 is shown X-address decoder 58 connected to XDCgates register 115. XDC gates register comprises four AND gates 59 whoseoutputs are connected to X-address decoder 58.

One input side of AND gates 59 is connected individually to line X(0-3)while the other side is connected in common to line XDC from statusregister SR(0) 108.

In a similar manner, FIG. 20 shows Y-address decoder 62 connected to YDCgates register 120. YDC gates register also comprises four ANDgates 63whose outputs are connected to Y-address decoder 62. A

One input side of ANDgates 63 is connected individually to lines Y'(0-3)while the other side is connected in common to line YDC from statusregister SR(0)108.

Typically, in FIG. 17 is shown X-address encoder 66 with outputconnected to multiple input OR gate XQOR and AND gates register XEC 81comprising all AND gates 67.It

1. A graphical input-output device for a computer comprising a pluralityof light emitter-sensor circuits juxtaposed in a common plane andarranged in ordered array, means for electrically activating anddeactivating said light emitters, means for emitting radiant energy foractivating said light sensors, means for connecting said emitter-sensorcircuits to a computer, and means for controlling the flow ofinformation represented by the activated and inactivated status of saidemitters from and to said computer.
 2. The graphical input-output devicefor a computer as claimed in claim 1 wherein said means for electricallyactivating and deactivating said light emitters includes means foridentifying by an address each emitter-sensor circuit according to acode, means for decoding a given address and activating said emitter atsaid address, means for encoding the address of an activated emitter andmeans for transmitting said encoded address to said computer.
 3. Thegraphical input-output device for a computer as claimed in claim 1wherein said means for electrically activating and deactivating saidlight emitters includes means for identifying by an address varioussub-pluralities of emitter-sensor circuits, means for activating saidemitters of said sub-pluralities, means for encoding said address andmeans for transmitting said encoded address to said computer.
 3. Thegraphical input-output device for a computer as claimed in claim 1wherein said means for controlling the flow of information representedbY the activated and inactivated status of said emitters comprises meansfor receiving information from said computer and distinguishing betweencontrol information and address information, and means for controllingthe flow of coded and decoded address information into and out of saidplurality of emitter-sensor circuits using said control information. 5.The graphical input-output device for a computer as claimed in claim 1wherein said plurality of light emitter-sensor circuits are arranged inrows and columns, said rows defining a Y-direction or coordinate andsaid columns defining an X-direction or coordinate.
 6. The graphicalinput-output device for a computer as claimed in claim 1 wherein saidmeans for activating said sensors is a penlight comprising a write endand an erase end, a light source at each of said ends, means foractivating said light sources, means for connecting said penlight tosaid means for electrically activating and deactivating said lightemitters and means for connecting said penlight to said means forcontrolling the flow of information from and to said computer.
 7. Thegraphical input-output device for a computer as claimed in claim 6wherein said penlight write end comprises means for marking a surfaceand said penlight erase end comprises means for removing marks made bysaid means for marking.
 8. The graphical input-output device for acomputer as claimed in claim 6 wherein said penlight comprises means forcontrolling the intensity of said light sources.
 9. The graphicalinput-output device for a computer as claimed in claim 1 wherein saidemitter-sensor circuit comprise means for maintaining said light emitterin the activated state when activated and in the deactivated state whennot activated.
 10. The graphical input-output device for a computer asclaimed in claim 9 wherein said means for maintaining said lightemitters in either the activated or deactivated state comprises apnp-npn transistor pair.
 11. The graphical input-output device for acomputer as claimed in claim 1 wherein said emitter-sensor circuitcomprises means for storing information concerning the activated andinactivated status of said emitter.
 12. The graphical input-outputdevice for a computer as claimed in claim 1 wherein said ordered arrayof said light emitter-sensor circuits comprises means for activating allof said emitters from a common circuit, means for deactivating all ofsaid emitters from a common circuit and means for detecting the statusof all of said individual emitters from a common circuit.
 13. Thegraphical input-output device for a computer as claimed in claim 1wherein said emitter-sensor circuits comprise means for detecting lightintensities by said light sensors and means for controlling the lightintensity emitted by said light emitters.
 14. The graphical input-outputdevice for a computer as claimed in claim 1 wherein said emitter-sensorcircuits comprise means for individually controlling the intensity oflight emitted by each of said light emitters.
 15. The graphicalinput-output device for a computer as claimed in claim 1 wherein saidemitter-sensor circuits comprise means for controlling the intensity oflight emitters.
 16. The graphical input-output device for a computer asclaimed in claim 1 wherein said light emitter-sensing circuits comprisemeans for emitting light, means for energizing said means for emittinglight and means for deenergizing said means for emitting light.
 17. Thegraphical input-output device for a computer as claimed in claim 16wherein said means for energizing said means for emitting lightcomprises means for detecting radiant energy and said means fordeenergizing said means for emitting light comprises means for detectingradiant energy.
 18. The graphical input-output device for a computer asclaimed in claim 16 wherein said means for energizing said means foremitting light comprises a transistor and said means for deenergizingsaid means for emitting light comprIses a transistor.
 19. The graphicalinput-output device for a computer as claimed in claim 16 wherein saidmeans for emitting light is a light emitting diode.
 20. The graphicalinput-output device for a computer as claimed in claim 16 furthercomprising means for detecting the activated or inactivated status ofsaid mean for emitting light.
 21. The graphical input-output device fora computer as claimed in claim 1 wherein said means for controlling theflow of information from and to said computer includes means forinterrupting the flow of information to said computer.
 22. The graphicalinput-output device for a computer as claimed in claim 1 wherein saidmeans for controlling the flow of information from and to said computercomprises a drawingboard processor unit, means for placing informationinto said array, and means for reading information represented by theactivated or inactivated status of said emitters out of said array. 23.The graphical input-output device for a computer as claimed in claim 22wherein said means for placing information into said array comprises aninput register having input and output lines, and an input partsregister having input and output lines, said output lines of said inputregister connected to said emitter-sensor array, said input lines ofsaid input register connected to said output lines of said input partsregister and said input lines to said input parts register connected tosaid processor unit.
 24. The graphical input-output device for acomputer as claimed in claim 22 wherein said means for readinginformation out of said array comprises an output register having inputand output lines an output parts register having input and output lines,and a drawingboard output register having input and output lines, saidinput lines of said output register connected to said array, said outputlines of said output register connected to said input lines of saidoutput parts register, said output lines of said output parts registerconnected to said input lines of said drawingboard output register andsaid output lines of said drawingboard output register connected to saidcomputer.
 25. The graphical input-output device for a computer asclaimed in claim 23 further comprising means for decoding addressesdefining a particular emitter-sensor circuit of said array having aninput and an output, said output connected to said input parts register,said input connected to said drawingboard processor unit.
 26. Thegraphical input-output device for a computer as claimed in claim 24further comprising means for encoding addresses defining a particularemitter-sensor circuit of said array having an input and an output, saidinput connected to said output register and said output connected tosaid drawingboard output register.
 27. The graphical input-output devicefor a computer as claimed in claim 22 wherein said drawingboardprocessor unit comprises means for receiving coded address and controlinformation from an incoming signal and distinguishing said addressinformation from said control information, means for decoding saidcontrol information having an input and an output, said input connectedto said means for receiving coded information, means for decoding saidaddress information having an input and an output, means forinterconnecting the output of said means for decoding of said controlinformation for control of flow of address information to said array ofsaid emitter-sensor circuits.
 28. The graphical input-output device fora computer as claimed in claim 26 wherein said drawingboard processorunit further comprises means for encoding address information inaccordance with the active or inactive status of said emitter-sensorcircuits of said array and means for interconnecting the output of saidmeans for decoding control information and said means for encoding saidaddress information for control of flow of address information out ofsaid array of emitter-sensor circuits to said computer.
 29. ThegraphicAl input-output device for a computer as claimed in claim 22wherein said drawingboard processor unit includes means for associatinga label with the activated or inactivated status of emitters in saidarray.
 30. The graphical input-output device for a computer as claimedin claim 22 wherein said drawingboard processor unit includes means forstoring address and control information for later use in operating saiddevice.
 31. The graphical input-output device for a computer as claimedin claim 22 wherein said means for reading information includes meansfor detecting incremental variations in graphical information displayedin said array.
 32. The graphical input-output device for a computer asclaimed in claim 30 wherein said drawingboard processor unit furthercomprises a primary input register for receiving address and controlinformation from said computer and means for transferring said addressinformation into said means for storing address and control informationand means for transferring address and control information out of saidmeans for storing address and control information to operate said array.33. The graphical input-output device for a computer as claimed in claim1 wherein said emitter-sensor circuit comprises means for controllingthe sensitivity of said light sensors to various levels of lightintensity.